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[VHDL-FPGA-VerilogDES_Verilog

Description: des加密算法verilog实现,包括模块定义,端口说明-des Encryption and decryption
Platform: | Size: 20480 | Author: 王彬 | Hits:

[OtherExample-s5-1

Description:  “\Example-s5-1\des” 目录下为设计工程,其设计输入采用Synplify预先编译好的.vqm网表  “\Example-s5-1\source”目录下为设计的源代码,这里只给出了Verilog语言实例,仅供读者参考  “\Example-s5-1\source \area_opt”目录下为面积优化的代码  “\Example-s5-1\source \perf_opt”目录下为性能优化的代码 “\Example-s5-1\source \common”目录下是共用的代码-Under  \ Example-s5-1 \ des directory for design engineering, the design input using Synplify precompiled .vqm netlist  \ Example-s5-1 \ source directory for the design of the source code, just to give examples of Verilog language, reference work  \ Example-s5-1 \ source \ area_opt directory for the area-optimized code Under  \ Example-s5-1 \ source \ perf_opt directory for performance-optimized code Under the \ Example-s5-1 \ source \ common directory is shared code
Platform: | Size: 126976 | Author: zhuchaoyong | Hits:

[VHDL-FPGA-VerilogDES_verilog

Description: 用verilog实现的DES(Data Encryption Standard数据加密标准),把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
Platform: | Size: 477184 | Author: 荣志强 | Hits:

[Otherdes_latest.tar

Description: 利用verilog实现的DES和3DES两种加密算法,其中每个算法又利用了两种实现方式,分别是面积优先和性能优先-Both use DES and 3DES encryption algorithms verilog implementation, which took advantage of each algorithm implemented in two ways, which are the priority and performance priority area
Platform: | Size: 41984 | Author: 程鹏 | Hits:

[Crack HackDES_orginal_core

Description: this a DES encryption code in verilog-this is a DES encryption code in verilog
Platform: | Size: 22528 | Author: tahmoures | Hits:
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